CCM Clock Gating Register 3
| CG0 | Reserved |
| CG1 | lpuart5 clock (lpuart5_clk_enable) |
| CG2 | semc clocks (semc_clk_enable) |
| CG3 | lpuart6 clock (lpuart6_clk_enable) |
| CG4 | aoi1 clock (aoi1_clk_enable) |
| CG5 | Reserved |
| CG6 | Reserved |
| CG7 | ewm clocks (ewm_clk_enable) |
| CG8 | wdog1 clock (wdog1_clk_enable) |
| CG9 | flexram clock (flexram_clk_enable) |
| CG10 | acmp1 clocks (acmp1_clk_enable) |
| CG11 | acmp2 clocks (acmp2_clk_enable) |
| CG12 | acmp3 clocks (acmp3_clk_enable) |
| CG13 | acmp4 clocks (acmp4_clk_enable) |
| CG14 | The OCRAM clock cannot be turned off when the CM cache is running on this device. |
| CG15 | iomuxc_snvs_gpr clock (iomuxc_snvs_gpr_clk_enable) |